AQFN

AQFN package

AQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

B0QFN

B0QFN package

B0QFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

B1QFN

B1QFN package

B1QFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

B3QFN

B3QFN package

B3QFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

Bare-Die

Bare Die package

Bare Die package belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

BCC

BCC package

BCC package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

BGA

Ball Grid Array

Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

BGA-100

Ball Grid Array (100 terminals)

100-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-144

Ball Grid Array (144 terminals)

144-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-169

Ball Grid Array (169 terminals)

169-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-196

Ball Grid Array (196 terminals)

196-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-256

Ball Grid Array (256 terminals)

256-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-400

Ball Grid Array (400 terminals)

400-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-484

Ball Grid Array (484 terminals)

484-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-64

Ball Grid Array (64 terminals)

64-terminal variant of Ball Grid Array. Ball Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

BGA-CSP

BGA CSP package

BGA CSP package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CBGA

Ball Grid Array (ceramic)

Ball Grid Array (ceramic) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CDFP

CDFP package

CDFP package belongs to the ceramic flat family. Its defining interconnection is ceramic body and flat leads. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CDIP

Ceramic Dual In-Line Package

Ceramic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CERDIP

Ceramic Dual In-Line Package

Ceramic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CFP

CFP package

CFP package belongs to the ceramic flat family. Its defining interconnection is ceramic body and flat leads. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CLCC

Ceramic Leadless Chip Carrier

Ceramic Leadless Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CLGA

Land Grid Array (ceramic)

Land Grid Array (ceramic) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

COB

Chip on Board

Chip on Board belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

COF

Chip on Film

Chip on Film belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

COG

Chip on Glass

Chip on Glass belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CPGA

Pin Grid Array (ceramic)

Pin Grid Array (ceramic) belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CQFP

Quad Flat Package (ceramic)

Quad Flat Package (ceramic) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

CSP

Chip Scale Package

Chip Scale Package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

D2PAK

Double Decawatt Package

Double Decawatt Package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

D3PAK

D3PAK package

D3PAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DFN

Dual Flat No-Lead

Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DFN-10

Dual Flat No-Lead (10 terminals)

10-terminal variant of Dual Flat No-Lead. Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DFN-12

Dual Flat No-Lead (12 terminals)

12-terminal variant of Dual Flat No-Lead. Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DFN-16

Dual Flat No-Lead (16 terminals)

16-terminal variant of Dual Flat No-Lead. Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DFN-6

Dual Flat No-Lead (6 terminals)

6-terminal variant of Dual Flat No-Lead. Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DFN-8

Dual Flat No-Lead (8 terminals)

8-terminal variant of Dual Flat No-Lead. Dual Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DFPAK

DFPAK package

DFPAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DHVQFN

DHVQFN package

DHVQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DIMM

DIMM package

DIMM package belongs to the bare die / module family. Its defining interconnection is die or module-level interconnect. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DIP

Dual In-Line Package

Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DIP-14

Dual In-Line Package (14 terminals)

14-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-16

Dual In-Line Package (16 terminals)

16-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-18

Dual In-Line Package (18 terminals)

18-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-20

Dual In-Line Package (20 terminals)

20-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-24

Dual In-Line Package (24 terminals)

24-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-28

Dual In-Line Package (28 terminals)

28-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-32

Dual In-Line Package (32 terminals)

32-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-40

Dual In-Line Package (40 terminals)

40-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DIP-8

Dual In-Line Package (8 terminals)

8-terminal variant of Dual In-Line Package. Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DirectFET

DirectFET package

DirectFET package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DPAK

Decawatt Package

Decawatt Package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DQFN

DQFN package

DQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

DQFN-14

DQFN package (14 terminals)

14-terminal variant of DQFN package. DQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DQFN-20

DQFN package (20 terminals)

20-terminal variant of DQFN package. DQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

DSBGA

DSBGA package

DSBGA package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

eLQFP

eLQFP package

eLQFP package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

eTQFP

eTQFP package

eTQFP package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FBGA

Ball Grid Array (fine-pitch)

Ball Grid Array (fine-pitch) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FCBGA

FCBGA package

FCBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FCFBGA

FCFBGA package

FCFBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FCQFN

FCQFN package

FCQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FDFN

Dual Flat No-Lead (fine-pitch)

Dual Flat No-Lead (fine-pitch) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FLGA

Land Grid Array (fine-pitch)

Land Grid Array (fine-pitch) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

Flip-Chip

Flip Chip package

Flip Chip package belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

FQFP

Quad Flat Package (fine-pitch)

Quad Flat Package (fine-pitch) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HQFP

Quad Flat Package (thermally enhanced)

Quad Flat Package (thermally enhanced) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HSOIC

Small Outline Integrated Circuit (thermally enhanced)

Small Outline Integrated Circuit (thermally enhanced) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HSOP

Small Outline Package (thermally enhanced)

Small Outline Package (thermally enhanced) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HTQFP

Thin Quad Flat Package (thermally enhanced)

Thin Quad Flat Package (thermally enhanced) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HTSSOP

Thin Shrink Small Outline Package (thermally enhanced)

Thin Shrink Small Outline Package (thermally enhanced) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

HVQFN

HVQFN package

HVQFN package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

I2PAK

I2PAK package

I2PAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

IPAK

IPAK package

IPAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

JLCC

J-leaded Chip Carrier

J-leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LCC

Leadless Chip Carrier

Leadless Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LFBGA

LFBGA package

LFBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LFCSP

Lead-frame Chip Scale Package

Lead-frame Chip Scale Package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LFPAK

LFPAK package

LFPAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LGA

Land Grid Array

Land Grid Array belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LQFN

Quad Flat No-Lead (low-profile)

Quad Flat No-Lead (low-profile) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LQFP

Low-profile Quad Flat Package

Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

LQFP-100

Low-profile Quad Flat Package (100 terminals)

100-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-128

Low-profile Quad Flat Package (128 terminals)

128-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-144

Low-profile Quad Flat Package (144 terminals)

144-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-176

Low-profile Quad Flat Package (176 terminals)

176-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-208

Low-profile Quad Flat Package (208 terminals)

208-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-32

Low-profile Quad Flat Package (32 terminals)

32-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-48

Low-profile Quad Flat Package (48 terminals)

48-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-64

Low-profile Quad Flat Package (64 terminals)

64-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

LQFP-80

Low-profile Quad Flat Package (80 terminals)

80-terminal variant of Low-profile Quad Flat Package. Low-profile Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

MCM

Multi-chip Module

Multi-chip Module belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MLF

Micro Lead Frame

Micro Lead Frame belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MLP

Micro Leadframe Package

Micro Leadframe Package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MLPA

MLPA package

MLPA package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MLPQ

MLPQ package

MLPQ package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MLPS

MLPS package

MLPS package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MQFP

MQFP package

MQFP package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MSOP

Mini Small Outline Package

Mini Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

MSOP-10

Mini Small Outline Package (10 terminals)

10-terminal variant of Mini Small Outline Package. Mini Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

MSOP-12

Mini Small Outline Package (12 terminals)

12-terminal variant of Mini Small Outline Package. Mini Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

MSOP-16

Mini Small Outline Package (16 terminals)

16-terminal variant of Mini Small Outline Package. Mini Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

MSOP-8

Mini Small Outline Package (8 terminals)

8-terminal variant of Mini Small Outline Package. Mini Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PBGA

Ball Grid Array (plastic)

Ball Grid Array (plastic) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PDIP

Plastic Dual In-Line Package

Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PDIP-14

Plastic Dual In-Line Package (14 terminals)

14-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-16

Plastic Dual In-Line Package (16 terminals)

16-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-20

Plastic Dual In-Line Package (20 terminals)

20-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-24

Plastic Dual In-Line Package (24 terminals)

24-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-28

Plastic Dual In-Line Package (28 terminals)

28-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-40

Plastic Dual In-Line Package (40 terminals)

40-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDIP-8

Plastic Dual In-Line Package (8 terminals)

8-terminal variant of Plastic Dual In-Line Package. Plastic Dual In-Line Package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PDSO

PDSO package

PDSO package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PGA

Pin Grid Array

Pin Grid Array belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PLCC

Plastic Leaded Chip Carrier

Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PLCC-20

Plastic Leaded Chip Carrier (20 terminals)

20-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-28

Plastic Leaded Chip Carrier (28 terminals)

28-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-32

Plastic Leaded Chip Carrier (32 terminals)

32-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-44

Plastic Leaded Chip Carrier (44 terminals)

44-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-52

Plastic Leaded Chip Carrier (52 terminals)

52-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-68

Plastic Leaded Chip Carrier (68 terminals)

68-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLCC-84

Plastic Leaded Chip Carrier (84 terminals)

84-terminal variant of Plastic Leaded Chip Carrier. Plastic Leaded Chip Carrier belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

PLGA

Land Grid Array (plastic)

Land Grid Array (plastic) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PoP

Package on Package

Package on Package belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PowerPAK

PowerPAK package

PowerPAK package belongs to the power family. Its defining interconnection is large thermal/electrical terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PowerSO

PowerSO package

PowerSO package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PPGA

Pin Grid Array (plastic)

Pin Grid Array (plastic) belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PQFN

Quad Flat No-Lead (plastic)

Quad Flat No-Lead (plastic) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PQFP

Quad Flat Package (plastic)

Quad Flat Package (plastic) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

PSOP

Small Outline Package (plastic)

Small Outline Package (plastic) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFI

Quad Flat I-lead

Quad Flat I-lead belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFJ

Quad Flat J-lead

Quad Flat J-lead belongs to the chip carrier family. Its defining interconnection is perimeter J-leads or lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFN

Quad Flat No-Lead

Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFN-16

Quad Flat No-Lead (16 terminals)

16-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-20

Quad Flat No-Lead (20 terminals)

20-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-24

Quad Flat No-Lead (24 terminals)

24-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-28

Quad Flat No-Lead (28 terminals)

28-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-32

Quad Flat No-Lead (32 terminals)

32-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-40

Quad Flat No-Lead (40 terminals)

40-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-48

Quad Flat No-Lead (48 terminals)

48-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-64

Quad Flat No-Lead (64 terminals)

64-terminal variant of Quad Flat No-Lead. Quad Flat No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFN-EP

QFN EP package

QFN EP package belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFP

Quad Flat Package

Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

QFP-100

Quad Flat Package (100 terminals)

100-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-128

Quad Flat Package (128 terminals)

128-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-144

Quad Flat Package (144 terminals)

144-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-176

Quad Flat Package (176 terminals)

176-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-208

Quad Flat Package (208 terminals)

208-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-44

Quad Flat Package (44 terminals)

44-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-64

Quad Flat Package (64 terminals)

64-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QFP-80

Quad Flat Package (80 terminals)

80-terminal variant of Quad Flat Package. Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

QSOP

Quarter-size Small Outline Package

Quarter-size Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-59

Small Outline SC-59

Small Outline SC-59 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-70

Small Outline SC-70

Small Outline SC-70 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-74

Small Outline SC-74

Small Outline SC-74 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-75

Small Outline SC-75

Small Outline SC-75 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-88

Small Outline SC-88

Small Outline SC-88 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SC-89

Small Outline SC-89

Small Outline SC-89 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SDIP

SDIP package

SDIP package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SIMM

SIMM package

SIMM package belongs to the bare die / module family. Its defining interconnection is die or module-level interconnect. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SIP

Single In-Line Package

Single In-Line Package belongs to the through-hole family. Its defining interconnection is single or staggered through-hole row. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SiP

System in Package

System in Package belongs to the bare die / module family. Its defining interconnection is assembly-level interconnect, not a universal PCB footprint. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SO

SO package

SO package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SODIMM

SODIMM package

SODIMM package belongs to the bare die / module family. Its defining interconnection is die or module-level interconnect. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOIC

Small Outline Integrated Circuit

Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOIC-14

Small Outline Integrated Circuit (14 terminals)

14-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-16

Small Outline Integrated Circuit (16 terminals)

16-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-18

Small Outline Integrated Circuit (18 terminals)

18-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-20

Small Outline Integrated Circuit (20 terminals)

20-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-24

Small Outline Integrated Circuit (24 terminals)

24-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-28

Small Outline Integrated Circuit (28 terminals)

28-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-8

Small Outline Integrated Circuit (8 terminals)

8-terminal variant of Small Outline Integrated Circuit. Small Outline Integrated Circuit belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SOIC-EP

SOIC EP package

SOIC EP package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOJ

Small Outline J-lead

Small Outline J-lead belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SON

Small Outline No-Lead

Small Outline No-Lead belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOP

Small Outline Package

Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-143

Small Outline Transistor SOT-143

Small Outline Transistor SOT-143 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-223

Small Outline Transistor SOT-223

Small Outline Transistor SOT-223 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-23

Small Outline Transistor SOT-23

Small Outline Transistor SOT-23 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-23-3

Small Outline Transistor SOT-23-3

Small Outline Transistor SOT-23-3 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-23-5

Small Outline Transistor SOT-23-5

Small Outline Transistor SOT-23-5 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-23-6

Small Outline Transistor SOT-23-6

Small Outline Transistor SOT-23-6 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-23-8

Small Outline Transistor SOT-23-8

Small Outline Transistor SOT-23-8 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-25

Small Outline Transistor SOT-25

Small Outline Transistor SOT-25 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-26

Small Outline Transistor SOT-26

Small Outline Transistor SOT-26 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-323

Small Outline Transistor SOT-323

Small Outline Transistor SOT-323 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-343

Small Outline Transistor SOT-343

Small Outline Transistor SOT-343 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-353

Small Outline Transistor SOT-353

Small Outline Transistor SOT-353 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-363

Small Outline Transistor SOT-363

Small Outline Transistor SOT-363 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-416

Small Outline Transistor SOT-416

Small Outline Transistor SOT-416 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-457

Small Outline Transistor SOT-457

Small Outline Transistor SOT-457 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-523

Small Outline Transistor SOT-523

Small Outline Transistor SOT-523 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-563

Small Outline Transistor SOT-563

Small Outline Transistor SOT-563 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-666

Small Outline Transistor SOT-666

Small Outline Transistor SOT-666 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-723

Small Outline Transistor SOT-723

Small Outline Transistor SOT-723 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-753

Small Outline Transistor SOT-753

Small Outline Transistor SOT-753 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-883

Small Outline Transistor SOT-883

Small Outline Transistor SOT-883 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-89

Small Outline Transistor SOT-89

Small Outline Transistor SOT-89 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SOT-953

Small Outline Transistor SOT-953

Small Outline Transistor SOT-953 belongs to the sot / sc family. Its defining interconnection is miniature perimeter leads or contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SPDIP

SPDIP package

SPDIP package belongs to the through-hole family. Its defining interconnection is two rows of pins (or single/staggered rows for SIP/ZIP). It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SSOP

Shrink Small Outline Package

Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

SSOP-16

Shrink Small Outline Package (16 terminals)

16-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-20

Shrink Small Outline Package (20 terminals)

20-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-24

Shrink Small Outline Package (24 terminals)

24-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-28

Shrink Small Outline Package (28 terminals)

28-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-48

Shrink Small Outline Package (48 terminals)

48-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-56

Shrink Small Outline Package (56 terminals)

56-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

SSOP-8

Shrink Small Outline Package (8 terminals)

8-terminal variant of Shrink Small Outline Package. Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TBGA

Ball Grid Array (thin)

Ball Grid Array (thin) belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TDFN

Dual Flat No-Lead (thin)

Dual Flat No-Lead (thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TFBGA

TFBGA package

TFBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-126

Transistor Outline TO-126

Transistor Outline TO-126 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-18

Transistor Outline TO-18

Transistor Outline TO-18 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-220

Transistor Outline TO-220

Transistor Outline TO-220 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-247

Transistor Outline TO-247

Transistor Outline TO-247 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-251

Transistor Outline TO-251

Transistor Outline TO-251 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-252

Transistor Outline TO-252

Transistor Outline TO-252 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-263

Transistor Outline TO-263

Transistor Outline TO-263 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-268

Transistor Outline TO-268

Transistor Outline TO-268 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-277

Transistor Outline TO-277

Transistor Outline TO-277 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-3

Transistor Outline TO-3

Transistor Outline TO-3 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-39

Transistor Outline TO-39

Transistor Outline TO-39 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-46

Transistor Outline TO-46

Transistor Outline TO-46 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-5

Transistor Outline TO-5

Transistor Outline TO-5 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-52

Transistor Outline TO-52

Transistor Outline TO-52 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-66

Transistor Outline TO-66

Transistor Outline TO-66 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-92

Transistor Outline TO-92

Transistor Outline TO-92 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TO-99

Transistor Outline TO-99

Transistor Outline TO-99 belongs to the transistor outline family. Its defining interconnection is metal or moulded body with terminals. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TQFN

Quad Flat No-Lead (thin)

Quad Flat No-Lead (thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TQFP

Thin Quad Flat Package

Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TQFP-100

Thin Quad Flat Package (100 terminals)

100-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-144

Thin Quad Flat Package (144 terminals)

144-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-32

Thin Quad Flat Package (32 terminals)

32-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-44

Thin Quad Flat Package (44 terminals)

44-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-48

Thin Quad Flat Package (48 terminals)

48-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-64

Thin Quad Flat Package (64 terminals)

64-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TQFP-80

Thin Quad Flat Package (80 terminals)

80-terminal variant of Thin Quad Flat Package. Thin Quad Flat Package belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSOP

Thin Small Outline Package

Thin Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TSSOP

Thin Shrink Small Outline Package

Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

TSSOP-14

Thin Shrink Small Outline Package (14 terminals)

14-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-16

Thin Shrink Small Outline Package (16 terminals)

16-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-20

Thin Shrink Small Outline Package (20 terminals)

20-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-24

Thin Shrink Small Outline Package (24 terminals)

24-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-28

Thin Shrink Small Outline Package (28 terminals)

28-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-32

Thin Shrink Small Outline Package (32 terminals)

32-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-38

Thin Shrink Small Outline Package (38 terminals)

38-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

TSSOP-8

Thin Shrink Small Outline Package (8 terminals)

8-terminal variant of Thin Shrink Small Outline Package. Thin Shrink Small Outline Package belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility. The suffix identifies terminal count, not a unique land pattern.

UDFN

Dual Flat No-Lead (ultra-thin)

Dual Flat No-Lead (ultra-thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

UFBGA

UFBGA package

UFBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

UQFN

Quad Flat No-Lead (ultra-thin)

Quad Flat No-Lead (ultra-thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

USON

Small Outline No-Lead (ultra-thin)

Small Outline No-Lead (ultra-thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

VFBGA

VFBGA package

VFBGA package belongs to the grid array family. Its defining interconnection is two-dimensional contact array. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

VQFN

Quad Flat No-Lead (very thin)

Quad Flat No-Lead (very thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

VQFP

Quad Flat Package (very thin)

Quad Flat Package (very thin) belongs to the quad leaded family. Its defining interconnection is four perimeter lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

VSOP

Small Outline Package (very thin)

Small Outline Package (very thin) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

VSSOP

Shrink Small Outline Package (very thin)

Shrink Small Outline Package (very thin) belongs to the small outline family. Its defining interconnection is two opposing lead banks. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

WCSP

Chip Scale Package (very thin)

Chip Scale Package (very thin) belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

WDFN

Dual Flat No-Lead (very thin)

Dual Flat No-Lead (very thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

WLCSP

Wafer-Level Chip Scale Package

Wafer-Level Chip Scale Package belongs to the chip scale family. Its defining interconnection is die-scale external contacts. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

WQFN

Quad Flat No-Lead (very thin)

Quad Flat No-Lead (very thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

WSON

Small Outline No-Lead (very thin)

Small Outline No-Lead (very thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

XDFN

Dual Flat No-Lead (extremely thin)

Dual Flat No-Lead (extremely thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

XQFN

Quad Flat No-Lead (extremely thin)

Quad Flat No-Lead (extremely thin) belongs to the leadless family. Its defining interconnection is underside perimeter lands. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.

ZIP

Zig-Zag In-Line Package

Zig-Zag In-Line Package belongs to the through-hole family. Its defining interconnection is single or staggered through-hole row. It is used where package size, assembly process, electrical parasitics, thermal management and connection density determine component selection. Pin arrangement, pad geometry, body dimensions and exposed-pad details must be taken from the exact manufacturer drawing; family-level naming does not guarantee footprint compatibility.